Profile

Prof. V. Ramgopal Rao is currently the Group Vice-Chancellor for the Birla Institute of Technology & Science (BITS) Pilani campuses located in Pilani, Hyderabad, Goa, Dubai and Mumbai. Prior to joining the BITS Group in 2023, Prof. Rao had served as the Director of IIT Delhi for 6 years during 2016-2021 and as a Chair Professor for Nanoelectronics at both IIT Bombay and IIT Delhi. Prof. Rao is an internationally acclaimed Nanoelectronics researcher with over 500 research papers and over 50 patents, which include 20 issued US patents. 15 of his patents have been licensed to industries for commercialization. The IP on CMOS-SoC applications developed in his group is now used in 100's of millions of ICs sold all over the world. Prof. Rao is a co-founder of two deep technology startups at IIT Bombay (Nanosniff&Soilsens) which have successful commercial products in the market. Besides his education and research activities, Prof. Rao is also well known for establishing major Nanoelectronics Programmes in India. For his research accomplishments, Dr. Rao has been elected a Fellow of IEEE, a Fellow of The World Academy of Sciences (TWAS), the Indian National Academy of Engineering (INAE), the Indian Academy of Sciences (IASc), the National Academy of Sciences (NASI) & the Indian National Science Academy (INSA). 52 Ph.D. students have graduated so far under his supervision and are working in leading academic institutions, semiconductor industries all over the world, including in India. Prof. Rao's research and leadership contributions have been recognized with over 35 awards and honors in the country and abroad. He is a recipient of three honorary doctorates. The recognitions Prof. Rao received include the Shanti Swarup Bhatnagar Prize in Engineering Sciences, Infosys Prize, IEEE EDS Education Award (the highest international award bestowed by IEEE Electron Devices Society for Education) and many others. Prof. Rao serves on the Editorial Advisory Boards of several leading international journals such as the ACS Nano Letters, AIP Applied Physics Reviews, IEEE Journal on Flexible Electronics etc. Dr. Rao has delivered over 200 Plenary, key-note and invited lectures all over the world.

Topic

TOPIC: Sensor Platforms & Affordable IoT Solutions for the Developing World

Abstract

IoT based sensor networks are seeing a massive growth the world over. However, the poor infrastructure facilities available in many of the developing countries and the extreme low-cost requirements pose a challenge for an increased penetration of these technologies in such environments. This calls for an innovation on the technology front in addition to developing a novel business model for their penetration. The requirement for IoT sensor platforms in these economies is however very critical in solving the needs of security, healthcare, agriculture, water, air quality monitoring etc. In this talk, we will discuss some of these challenges and opportunities for development of IoT based sensor solutions for resource constrained environments. We will show the need for a massive deployment of such technologies, their calibration, power supply and network challenges as well as the user interface requirements keeping in mind the socio-economic conditions of the end users. In order to achieve some of these goals, we demonstrate novel sensor integration methodologies where completely diverse platforms, materials and approaches are brought together in order to realize the desired system functionality at the targeted price points. The talk also discusses how nano-scale materials and phenomena can help improve the sensitivity of sensor platforms for detection of sub ppb levels of analytes for specific sensing applications. that can enable our institutions to significantly contribute to India's Atmanirbhar Bharat mission.

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Sensor Platforms & Affordable IoT Solutions for the Developing World

Profile

Professor in electronics engineering at Digital University Kerala, and as the Chief Scientist and CTO at Graphene Aurora, He lead the research and development of cutting-edge graphene-based devices and neural chips for various applications, such as biomedical, IoT, and AI. With over 20+ years of experience in the field of electrical and electronics engineering, He had developed multiple patents, publications, and products that have advanced the state-of-the-art in brain-inspired computing. Areas of current work: AI chips (Memristors, Crossbars, Neuromorphic circuits, ANN, SNN, CNN, LSTM, HTM, LLMs), RF circuits, antenna designs (UWB, Phased Array Antennas, Parabolic Antennas, Horn Antennas, Log-Periodic Antennas, Patch (Microstrip) Antennas, Yagi-Uda Antennas, Spiral Antennas, Helical Antennas, and Monopole Antenna), various 2D materials (Graphene), Memory circuits (ReRAMs, STTRAM, PCM), drones, image processing, AI/ML, learning circuits, security circuits, impedance matching, crosstalk, and signal reflections, jitter and timing analysis, EMI and EMC

Topic

Crossbar based Mixed-Signal Neural Architectures under Variability and Parasitics

Abstract

In this lecture, the variability impact, compensation techniques, and variability-aware neural architectures are discussed. Variability and paracitics pose significant challenges in ensuring accurate multiply and accumulate (MAC) computations emulated with a crossbar. In most neural networks, the MAC forms the core computing module to implement a neuron and, consequently, neural networks. The analog MAC blocks are particularly susceptible to variability and parasitics, which can result in inaccuracies in the computation process. Therefore, developing techniques to mitigate these challenges is crucial for the successful implementation of variability averse mixed-signal neural architectures.

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Intricacies of mixed signal IC design

Abstract

Tate of the art SoC mandates mixed signal ICs to be designed with utmost sensitivity. The scaled down technologies throw severe bottlenecks in the design of mixed signal ICs as the design requirements for analog and digital subsystems do differ. The proposed talk aims to discuss the significance of mixed signal ICs and intricacies of the design of the same including deft lay out tips and design topologies for power management.

Profile

Dr. Deepak Mishra is Scientist/Engineer-SG and Head of Navigation Payload Electronics Division at Space Applications Centre (SAC), Indian Space Research Organization (ISRO), Ahmedabad, India. He has received Ph.D. degree from Indian Institute of Technology (IIT), Banaras Hindu University (BHU) on the topic “Joint Source Channel Coding for Deep Space Application”, in the year 2012. He received his M.Tech degree in Communications Systems Engineering from the Department of Electronics Engineering, IIT, B.H.U. in 2003 and B.E degree in Electronics and Communication from the Govt. G.B.Pant. Engineering College, Uttarakhand, India in 2001. He is associated with SAC, ISRO since the year 2003. During this tenure, he has been involved in various subsystems development of various ISRO projects. Currently, he is involved in the design and development of payload for NavIC systems, as an Associate Project Director in Technology demonstration payload (TDS-01) and as a focal person communication module for Gaganyaan project . He has more than 65 papers in various international journals and conferences. He has also delivered invited talk in International Conference at Tokyo University, Japan in 2016. He has 4 patents and 3 copyrights to his credit. He is the focal person for signal processing module of post graduate course of United Nation Satcom course and faculty member in the navigation systems course. He is a fellow of various academic institutes like IETE, IEI, ASI and ISSE. He is appointed in the Board of advisory members of MATHWORKS India. He is also an ISO 17024:2012 certified project manager. He is approved PhD guide at IISc Bangalore, IIT Gandhinagar, Gujarat University and Nirma University, Ahmedabad and currently 4 PhD candidate are working with him.

Topic

Use of VLSI for Signal Processing in Satellite Designs and its Applications

Abstract

VLSI technology plays a pivotal role in various aspects of space missions, offering diverse and extensive applications. One of its primary uses is in the design and development of communication systems, which facilitate data transmission between Earth and spacecraft, as well as among internal spacecraft components. By enabling the integration of complex communication modules—such as transceivers and signal processors—onto a single chip, VLSI technology ensures efficient and reliable communication in the challenging environment of space. In navigation and control systems, VLSI technology is equally indispensable. These systems guide and maneuver spacecraft during different mission phases. By integrating sensors, processors, and actuators onto compact VLSI chips, navigation and control systems achieve greater efficiency and miniaturization. This compactness not only enhances spacecraft design flexibility but also allows for precise and reliable control of spacecraft movements. Another critical application of VLSI technology in space missions lies in scientific instrumentation. VLSI chips enable the creation of highly sensitive and accurate sensors for measuring physical and chemical parameters. These advanced sensors are vital for collecting and analysing scientific data, supporting the study of celestial bodies, atmospheric conditions, and other phenomena, thereby advancing our understanding of the universe.In this presentation a details overview of VLSI technology used for signal processing applications in ISRO various projects will be presented. A part from that some standard practices and verification model of VLSI design will be discuss and presented

Profile

Ramanujam started his career with TI India as Analog design engineer in 1993. Through his career, he has led multiple product development teams and brings with him a wealth of functional expertise spanning across design, systems, applications and product line management. In the recent past he has been actively involved in the New College Graduate trainings and has conducted hardware hackathons in multiple colleges in India. Currently in the role of Global Technical Talent Lead, he is working on the strategy for technical talent development. In his free time, Ramanujam likes to engage in career counselling and is working on getting his accreditation as Associate Certified Coach. Ramanujam has a masters degree from IIT Kharagpur in Integrated Circutis and Systems Engineering and bachelors degree from Osmania University in ECE.

Topic

Career Opportunities in the fascinating world of Semicounductors

Abstract

Through the prism of an end-application and its system design, the author will bring out the different facets of VLSI chip development and how each function is critical to the development of a chip. Author will also try to establish the connect between the system design and the foundational courses that students take in their academia. This will be followed by different functional roles that are available as careers in the world of VLSI chip design and how each function is critical for making the product a success.

Profile

Rajesh Gupta, CEO MOSart Labs, leading higher education institution in advanced technology training in partnership with IIT, BBS. B-Tech in EEE (JEE AIR 127) from IIT, Madras where he won the Ramasarma Kolluri Medallion for best academic performance. M.S. in ECSE from RPI, NY USA, where he won the Henry J. Nolte Award for best academic performance and a promising future. His first full time job at Rockwell Scientific researching high-speed, high-power Si and compound semiconductor devices, followed by TRAM Inc, that was later acquired by Micron. In 2012 he moved back to India as the site leader and engineering head for Micron India R&D in Bangalore. India. In 2019, he joined ams India, as the country head and Sr. Director of R&D Engineering he successfully lead the development of several sensor products owned by the India design team, followed by successful commercialization for the business. A prolific inventor, he has more then 25 international patents to his credit.

Topic

Cross-functional systems Engineering

Abstract

While advances in electronics has powered numerous new applications, modern hardware is now increasingly complex and getting more so with time. Features of individual components now interact and influence the behavior of other components in the system. This has lead to increased interest in this new area called systems engineering dealing with optimizong the system as a whole by identifying new ways to design and pit together individual components to extract the maximum performance at the best cost. This field is multidisciplinary, involves understanding optics, mechanics, thermodynamics and several area of electronics. I would like to share some recent case studies into how this multidisciplinary approach is helping design more optimal electronics.

Profile

Dr. A .G. Krishna Kanth is the Founder and CTO of MOSart Labs, a VLSI edutech company founded for upskilling ECE & EEE students in the field of semiconductor technology and chip design. He served as the Director of Analog Mixed-Signal R&D at AMS semiconductors. He is an IEEE Senior member and currently the Vice-Chair for IEEE CAS/EDS Hyderabad Chapter and is frequently involved in delivering technical lectures at various Universities. He received his PhD from IIIT Hyderabad. He finished his B.Tech and M. Tech from IIT Bombay with Specialization in Microelectronics. He was awarded President of India Shankar Dayal Sharma gold medal and IIT Bombay Student Roll of Honour in 2002. Analog IC Design is his passion and his specialization includes sensors and sensor interfaces, high performance analog signal processing, power management for automotive and consumer semiconductor IC design. He worked earlier with Texas Instruments Bangalore and Qualcore Logic Hyderabad leading the Analog IC design teams. He is an adjunct professor at IIT Hyderabad and Digital University Kerala. He is on Academic council and BoS member at several universities. He has 13 patents and 11 IEEE publications. He is an Associate Editors for TCAS-II for 2024 & 2025.

Topic

CMOS Power Management Integrated Circuits for Automotive applications

Abstract

Automotive and EV industry is one of the key focus areas of Indian semiconductor Mission. With booming number of electric vehicles and semiconductors gaining more and more traction into automobiles, automotive electronics has grown into a vast field with lot of scope for research in design and process technology. The present talk would focus on power management integration circuits that can be used for automotive application. Patented Hybrid architecture of DC-DC converter and LDO with adaptive load biasing technique will be discussed as an alternative to build energy efficient circuits.

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Recent Trends in Indian Semiconductor IC Design

Topic

IO Design for Digital, Analog, Mixed-Signal ICs

Abstract

IO pad design plays a pivotal role in ensuring the performance, reliability, and functionality of Integrated Circuits (ICs) across digital, analog, and mixed-signal domains. This process involves addressing critical challenges such as Electrostatic Discharge (ESD) protection, signal integrity, power delivery, and speed optimization. Tailored design strategies are essential to meet diverse application requirements, including high-speed data transmission, noise reduction, and compatibility with advanced semiconductor technologies. This session provides innovative approaches and best practices for designing robust and efficient IO pads, highlighting their impact on IC performance and reliability in modern electronics

Profile

Sanjeev Srivastava is a Senior Digital Transformation Leader with over 30 years of experience in Digital Transformation, Global Customer Success Delivery, Engineering and Design and Development . Sanjeev Srivastava is Founder Director of ZOICX Technologies Pvt. Ltd. Based out of Hyderabad , India. He received his MS in Microlectronics Technology and Manufacturing Management from Ecole Nationale Superior de Mine St Ettienne France. He is an Alumni of College of Engineering- Osmania University and completed his undergrad in Electronics and Instrumentation in 1994. He completed his MBA in operations management from IGNOU-Delhi in 1999 and his Executive Management Program in Data Sciences from IIM-Luncknow in 2019. He worked in R&D departments of various leading Electronic Design companies before joining Synopsys in 2000. At Synopsys, he started his career in Design Services department before moving to the Global Technical Services organization in 2002. He has built and lead a strong team of Applications Engineer for delivering technology services for their global and Indian clients. Sanjeev has a Proven record of building high performance team, maintaining strong technical and working relationships with customers, field teams, BU and internal support organizations in India, S. Korea, Japan, Taiwan, S. Europe and Vietnam. Sanjeev is adjunct professor at OU-College of Engineering- Hyderabad and is also active on the BoS of the ECE department of the OUCE-Hyderabad.

Topic

Silicon Carbide/Gallium Nitride : Powering the future of the Indian SemiCon Industry

Abstract

India is taking significant strides to establish itself in the global semiconductor market. While the country has historically relied on imports for semiconductor devices due to the absence of local fabrication facilities, it is now embarking on a transformative journey. With increasing focus and efforts, India is positioning itself to become a valuable hub for semiconductor manufacturing in the years to come, paving the way for innovation and self-reliance in this critical sector. We are unlocking the future of semiconductors by focusing on niche technologies like gallium nitride and silicon carbide-based semiconductor device manufacturing as they have high demand across diverse industries like EV, Power conversion, Defence, 5G etc both in India and globally, we are poised to emerge as global leaders in these cutting-edge solutions.

Profile

Balaji Jayaraman received the B.E degree in Electronics and Communication Engineering from Osmania University, Hyderabad in 2004, and PhD degree from Indian Institute of Science (IISc), Bangalore in 2011. Prior to joining Micron in March 2021, he had 11+ years of experience working on 22nm embedded DRAM Health of the Line characterization and yield analysis (at IBM SRDC, India), charge-trap-transistor (CTT) based non-volatile memory design (at GlobalFoundries (GF), India). He is an IEEE Senior Member and holds 9 US patents (3 more in application state, and 1 more approved for filing). He has authored / co-authored 3 IEEE journal and 4 IEEE conference publications. He is the recipient of CEO recognition award at GF for the year 2018. At Micron, he is part of the DRAM design team at Hyderabad, leading the design effort on low power DRAM (LPDRAM). His research interests include embedded memory design and analog/digital circuit design.

Topic

DRAM: Applications, Design and Future Trends

Abstract

With the advent of generative AI, there is an increased demand for large amount of data being made available to the data centers and processing units. This talk provides an overview of the DRAM and the various applications that it caters to, including mobile, laptops, servers, datacenters. The talk provides a birds-eye view of the DRAM design starting from the bit-cell to the JEDEC defined LPDDR4 and LPDDR5, the latest generations of DRAM designs catering to the mobile markets. The talk would also focus on the technology scaling and the associated challenges. A brief overview of the latest trends and the state-of-the-art in the DRAM design would also be shared along with some insights into the future trends.

Topic

Hurdles and Horizons in Indian Semiconductor Industry

Abstract

The world of Very Large-Scale Integration (VLSI) design engineering is at the brink of significant transformations as we enter the era of semiconductor excellence. With the latest emerging trends and opportunity in VLSI design, it is evident that we are at the cusp of exciting developments. With the advancements in AI and Machine Learning to the advent of 5G and IoT technologies, from Quantum computing to Edge Computing, the future of VLSI technology holds immense promise. These emerging VLSI trends have led to creating Semiconductor Integrated Circuits (ICs) having multi-million of transistors into a single chip. But this has also introduced a multifaceted challenge in IC designing that involves addressing a balance between power, performance, area, and cost. As the complexity of designs advance, the ‘hurdles’ in semiconductor IC design become increasingly complex, requiring innovation in materials, tools, design methodologies, and architectural strategies. The IC design hurdles also come with vast array of opportunities in unlocking the future technological landscape. The new Horizons in Semiconductor industry evolved around Scaling beyond Moore’s law with 3D-ICs & Heterogenous Integration, Advanced node shrinking, Chiplet based designs, Security focused designing and Sustainability in IC design. In this session we cover the Hurdles and Horizons that are in the forefront of Semiconductor Industry and how India’s semiconductor landscape is undergoing a significant transformation, driven by government initiatives and strategic partnerships aimed at establishing the country as key player in global semiconductor industry.

Profile

Alumni from IIIT-Hyderabad (International Institute of Information Technology Hyderabad) Qualification: Post Graduate (M. Tech) in VLSI & Embedded Systems from IIIT-Hyderabad

Topic

High-Performance Data Transfers over Compute Express Link (CXL)

Abstract

This topic focuses on how CXL enables high-speed, low-latency data transfers, reshaping memory access, bandwidth utilization, and compute performance in next-generation systems. It could cover the technical innovations in CXL that facilitate efficient data movement across processors, memory, and accelerators, highlighting CXL's role in data-intensive applications such as AI/ML, real-time analytics, and cloud computing. Additionally, the talk could address the evolving CXL ecosystem and the potential impact on data center efficiency and scalability. This would give the audience insights into both the practical applications and underlying technology driving high-performance transfers over CXL.